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> 20 pcs. cypress# CY7C4211-25JC, 512X9 synchronous fifo
20 pcs. cypress# CY7C4211-25JC, 512X9 synchronous fifo
This item includes the following: 20 pcs. CYPRESS# CY7C4211-25JC. Parts are New/unused and ready for use. As always, we will are willing to look at all Best offers! Keep an eye on our store as our Inventory changes daily!
High-speed, low-power, first-in, first-out (FIFO)
High-speed 100-MHz operation (10 ns read/write cycle
Fully asynchronous and simultaneous read and write
Empty, Full, and Programmable Almost Empty and
Independant read and write enable pins
Center power and ground pins for reduced noise
Space saving 7mm x 7mm 32-pin TQFP
Pin compatible and functionally equivalent to IDT72421,
72201, 72211, 72221, 72231, 72241
THe CY7C42X1 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 9 bits wide. The CY7C42X1 are pin-compatible to
IDT722X1. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety
of data buffering needs, including high-speed data acquisition,
multiprocessor interfaces, and communications buffering.
These FIFOs have 9-bit input and output ports that are controlled
by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and two write-enable
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read-enable pins (REN1, REN2). In addition, the CY7C42X1
has an output enable pin (OE). The read (RCLK) and write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
