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EP2C5 fpga/sopc(niosii) development board lcd kit V3.0
EP2C5NiosIILearningDevelopmentKitV3.jpg picture by susie-one
1, FPGA core board: choice of a variety of core board (the core board information and pictures please contact us), what are the FPGA are:
(1) Cyclone core: EP1C12Q240C8, EP1C6Q240C8;
(2) CycloneII core: EP2C8Q208C8, EP2C5Q208C8, EP2C20Q208C8;
(4) Flash: 2Mbyte or 8Mbyte (only EP2C20), (factory configured to 2M byte sufficient to meet most needs. Designed to support the 4M Byte, any special needs, the user may need to replace their own 4M byte, such as AM29LV320) ;
(5) EPCS1 or EPCS4 configuration chip: EP1C6 and EP2C5 core board with EPCS1; EP1C12 and EP2C20 EP2C8 and core board with EPCS4;
(6) provides configuration mode: JTAG and AS. In addition, configure the pin through the pin leads, designed to support users in the future to use CPLD + Flash configuration mode;
(8) All IO, Avalon bus, and so on through four row configuration pin pin leads, users can play full freedom to expand more flexible;
(9) FPGA power supply system;
In the experimental plate 3.0:
RS-232 serial port: used for computer data communications;
VGA Interface: VGA and display direct connection of VGA interfaces with FPGA implementation protocol can be displayed in the display text, graphics, etc.;
PS / 2 mouse, keyboard interface: standard mouse, keyboard interface, providing the routine use of VHDL in the digital control to achieve at the same time show the keyboard scan code and ASCII code, it can also be combined with SOPC programming displayed on the LCD;
16 * 2 character LCD: can display English characters and custom characters;
128 * 64 graphic LCD: can display Chinese, graphics, etc.;
Buzzer: Use NIOSS II timer interrupt programming to produce a specific waveform, can play the variety of music such as: the North scenery, Kangding Love Song ...
(1) Use USB-UART bridge chip CP2102, compatible with USB1.1 and USB2.0 protocol, the maximum transmission rate is 1Mbps, can be used for communication speed requirement is not high occasions, such as industrial equipment, instrumentation, etc. convenient and practical; developers do not understand the USB protocol and design of the driver, just like the serial port shares the communications of operation can thus make short development period, the risk of small, low cost; In addition, its small size, anti-jamming performance, work stable, normal operating temperature range: -40 ~ +85 . With the CD package, comes with the chip's data sheet, drivers, and example programs.
4 digit 7-segment digital tube: NiosII respectively with VHDL and dynamic scanning procedure, using VHDL for automatic dynamic scanning, do not take up CPU processing time.
4 buttons switch: as adhering to the simple style, not the pursuit of more, but for simplicity, IO saving limited resources, the external key input for NiosII, interruption experiments suffice.
3, ByteBlasterII download cable, USB-Blaster download additional lines replaced (fully compatible with original Altera USB-Blaster) plus a 180 can.
Fourth, other accessories:
(2) 5V switching power supply;
(4) a full range of software (QuartusII5.1 and NiosII IDE5.1 Edition, etc.), documentation, etc.;
(5) detailed circuit diagram (pdf format);
(6) 16x2-type LCD modules;
(7) 128x64 Dot LCD module, 80;
(8) 10M network expansion module, 150;
(9) 100M network expansion module, 480;
(10) USB2.0 expansion module, 380;
5, development environment and software information:
(1) support and provide the latest QuartusII5.1 and NiosII IDE;
(2) Support SOPC Builder5.1;
(4) NIOS II IDE integrated development environment to support C / C + +, support ByteBlasterII and USB-Blaster-line running and debugging;
(6) nios-Linux Development Kit;
The model core board FPGA resource tables
Model EP1C6 type EP1C12 type EP2C5 type EP2C8 type
Les 5,980 12,060 4,608 8,256
RAM bits 92,160 239,616 119,808 165,888
None None 13 18 embedded multipliers
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