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Celoxica rc htx-vx 4 virtex 4 fpga htx accelerator


Link to spec datasheet: http://www.hypertransport.org/docs/tech/rchtx_datasheet_screen.pdf
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Xilinx Virtex-4 FPGA for Application Acceleration
- XC4VLX160 or XC4VSX55 device
- Custom hardware co-processing for AMD Opteron systems
- Fully programmable from Celoxica software compilation tools
- Direct access to entire host system memory space
- Kernel FPGA manages I/O tasks and frees user FPGA for co-processing
- 9.6 GB/sec max transfer rates
FPGA based hardware acceleration can provide dramatic performance improvements for the compute intensive algorithms frequently
Until now, the application of FPGA hardware to these problems has been hampered by poor communications bandwidth between
the host system and the FPGA and by the size and capability of the FPGA devices available. The architecture of the board solutions
available also required application developers to become involved in non-application areas such as I/O drivers.
The RCHTX HPC board provides solutions to these problems:
The HTX interface to the host system offers a potential communications bandwidth of 3.2 GBytes/s.
HTX provides direct access to the entire host system memory space.
RCHTX uses Xilinx Virtex-4 FPGAs offering high gate count, advanced dedicated arithmetic units and high clock speeds.
The RCHTX architecture insulates the application developer from I/O and driver issues by using a kernel FPGA to interface to the
host system and to provide control and management of data streaming between the host processor and the on-board memories.
When these features are coupled with Celoxica C-to-FPGA software compilation technology, the RCHTX becomes an ideal platform for
accelerated computing development and solution deployment.
The RCHTX HPC board provides the following functionality:
- Xilinx Virtex-4 XC4VLX160 or XC4VSX55 FPGA
- Gigabit Ethernet port (PHY only, requires soft MAC)
- 8 user-controllable status LEDs
- Flash memory for Kernel and User FPGA programming
HTX bus 16-bit data path running in either the 200MHz or 400MHz HyperTransport mode
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RCHTX Kernel FPGA Functionality
Provides a HyperTransport interface to the host processor. The kernel FPGA acts as a HyperTransport cave device.
Supports programming of the user FPGA by streaming bit files either from the host processor directly, from the host processor s
memory space, from the SRAM or from the flash memory.
Provides a streaming interface to the user FPGA. The streaming interface makes use of the SRAMs for caching and/or to
implement a shared memory space.
Provides a packet link to the user FPGA. The packet interface allow both the user FPGA to be mapped into the processor s virtual
memory space (slave), and the user FPGA to access the processor s memory space (master).
Perform FIFO buffering of virtual channels with a simple almost full/data valid protocol for streamed communications between the
The RCHTX is provided with a host PC library and utility (Linux)
Board memory capture (requires bit file replacement)
Also provided is a library for the user FPGA implementing simple
Local and kernel memory access
Console (text style) display to video output



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